HARDWARE DESIGN OF MESSAGE PASSING ARCHITECTURE ON HETEROGENEOUS SYSTEM

Heterogeneous multi/many-core chips are commonly used in today’s top tier supercomputers. Similar heterogeneous processing elements — or, computation ac- celerators — are commonly found in FPGA systems. Within both multi/many-core chips and FPGA systems, the on-chip network plays a critical role by connecting these processing elements together. However, The common use of the on-chip network is for point-to-point communication between on-chip components and the memory in- terface. As the system scales up with more nodes, traditional programming methods, such as MPI, cannot effectively use the on-chip network and the off-chip network, therefore could make communication the performance bottleneck. This research proposes a MPI-like Message Passing Engine (MPE) as part of the on-chip network, providing point-to-point and collective communication primitives in hardware. On one hand, the MPE improves the communication performance by offloading the communication workload from the general processing elements. On the other hand, the MPE provides direct interface to the heterogeneous processing ele- ments which can eliminate the data path going around the OS and libraries. Detailed experimental results have shown that the MPE can significantly reduce the com- munication time and improve the overall performance, especially for heterogeneous computing systems because of the tight coupling with the network. Additionally, a hybrid “MPI+X” computing system is tested and it shows MPE can effectively of- fload the communications and let the processing elements play their strengths on the computation

The mining of high risk equipment based on the algorithm of HR-Tree’s decision

Due to the different construction of various subsystems in the power grid, the information of various systems are not closely connected. Nowadays, the network is complex and changeable where the automation is getting higher. This article takes high-risk equipment set of substation in Liaoyang as the research background. It constructs HR-Tree for the device set, and establishes a high-risk equipment evaluation system which based on the HR-Tree context. Then we calculate high-risk equipment sets in the structure of overall data set. By establishing the original data set and the prior knowledge system of equipment risk, the non-candidate high-risk equipment set is reduced in the local path of the high-risk equipment set. We refer to the process of reducing data as minus branch. After the threshold is established, the branches are reduced and the highest risk equipment set is obtained. Finally, we use the scoring system to find the probability of occurrence of associated devices, such information is more open. Example showed that such methods could effectively express high-risk device sets, and managers could get early warning information based on this. It helps people monitoring the power system, w hich could also provides new ideas for the monitoring project

An Evaluation of an Integrated On-Chip/Off-Chip Network for High-Performance Reconfigurable Computing

As the number of cores per discrete integrated circuit (IC) device grows, the importance of the network on chip (NoC) increases. However, the body of research in this area has focused on discrete IC devices alone which may or may not serve the high-performance computing community which needs to assemble many of these devices into very large scale, parallel computing machines. This paper describes an integrated on-chip/off-chip network that has been implemented on an all-FPGA computing cluster. The system supports MPI-style point-to-point messages, collectives, and other novel communication. Results include the resource utilization and performance (in latency and bandwidth)